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Single
ME LCT trigger incl Q3,4, core logic running in //. No DT singles but DT
stubs to core ok. Max/Min eta unset. Accellerator muon and min d-phi cuts
set(first time). Timings are CSC local as of end May 08. LUTs are cmssw
200. Firmware all chips is 080408. BXA is on( BXA_depth=2).
Keys were created just before the June 2008 'CRUZET II'
Global Run.
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>LUT path stem will be:
bin/cmssw_2_0_0
> firmware versions
SP SP 08/04/08
SP FA 08/04/08
SP DD 08/04/08
SP VM 08/04/08
CCB MAIN 05/03/07
MS MAIN 26/06/07
> STATIC CONFIG
CSR_REQ SP MA 0x801f //trig core + singles. No DT
singles
ACT_HR VM MA 0x0001 //soft reset
CSR_SCC SP MA 0x0232 //(core vers==1):: BXA on, Q3,4
stubs allowed to core, Pre Trig==2
CSR_DFC DD MA 0x07ff // 7
TBINs, Zero suppr, All FFPGAs active, DT active, SP active, DDU readout
mode.
CSR_BID DD MA 0x8606 //configuration date is 6/6/08
CSR_MWC SP MA 0x0002 //MS winners clock phase ==2,
enable output to MS.
CSR_BSY VM MA 0x0041 //VM and DDU chip into BSY FMM
mask
CSR_RDY VM MA 0x0041 //VM and DDU chip into RDY FMM
mask
CSR_OSY VM MA 0x0041 //VM and DDU chip into OSY FMM
mask
CSR_WOF VM MA 0x0041 //VM and DDU chip into WOF FMM
mask
>TIMING CONFIG:: use timing as Mar, Apr 08 local
runs
CSR_REQ VM MA 0x0000 //No extra delay for L1-req
CSR_AFD FA MA 0x0558 //ME AFD == 0x58, ME1 offset=0x5
CSR_AFD SP MA 0x0504 //ME1 offset==0x5, delay incoming
MB by 0x4
CSR_PFD SP MA 0x0046 //PFD ==0x46
CSR_PFD FA MA 0x0046 //PFD ==0x46
> ETA CONFIG, set some pointing in core logic using
del-eta==0xff for all extraps(open)
CNT_ETA SP MA 0x0000 //reset ETA counter
DAT_ETA SP MA 0x0000 // ETA MIN; ME1-->ME2
DAT_ETA SP MA 0x0000 // ETA MIN; ME1-->ME3
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->ME3
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->ME4
DAT_ETA SP MA 0x0000 // ETA MIN; ME3-->ME4
DAT_ETA SP MA 0x0000 // ETA MIN; ME1-->ME2-ov
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->MB1
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->MB2
**depracated
DAT_ETA SP MA 0x007f // ETA MAX; ME1-->ME2
DAT_ETA SP MA 0x007f // ETA MAX; ME1-->ME3
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->ME3
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->ME4
DAT_ETA SP MA 0x007f // ETA MAX; ME3-->ME4
DAT_ETA SP MA 0x007f // ETA MAX; ME1-->ME2-ov
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->MB1
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->MB2
**depracated
DAT_ETA SP MA 0x00ff // ETA WIN; ME1-->ME2
DAT_ETA SP MA 0x00ff // ETA WIN; ME1-->ME3
DAT_ETA SP MA 0x00ff // ETA WIN; ME2-->ME3
DAT_ETA SP MA 0x00ff // ETA WIN; ME2-->ME4
DAT_ETA SP MA 0x00ff // ETA WIN; ME3-->ME4
DAT_ETA SP MA 0x00ff // ETA WIN; ME1-->ME2-overlap
**depracated
// set the 4 new
params
DAT_ETA SP MA 0x0002
DAT_ETA SP MA 0x0004
DAT_ETA SP MA 0x0010
DAT_ETA SP MA 0x0040
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Differences of
the four sets of keys:
#1
baseline trigger key(as shown above); 60608
- eta-win=0xff (open), for all track types. BXA on.
#2 open window only key; 70608
-as above but reset CSR_REQ/SP (CSR_REQ SP MA =0x8000)
so that only trigger on the core. (with open windows)
.
#3 closed window only key; 80608
-as #2 but set the eta windowin DAT_ETA to 0x5.
#4 open window, BXA off.:90608
-as #2 but turn off the BXA. (CSR_SCC=0x230).
Corresponding
emulator cfg files:
60608 cmssw config file
70608 cmssw config file
80608 cmssw config file
90608 cmssw config file
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