Configuration Keys
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-->7 Keys made on 120808(for CRUZET4)

-->Key 20708

-->Keys 20080606

-->Key 240408

-->Key 60308

 

 

 

 

 

 

 

 

Key "240408"; created 24/4/08

 

240408: Synopsis;

Single ME LCT trigger incl Q3,4, core logic running in //. No DT singles but DT stubs to core ok. Max/Min eta unset but eta-win=5 for all track types. BXA off. Accellerator muon and min d-phi cuts as default. Timings are CSC local as of Mar/Apr 08, approx ~7bx faster than expected CMS L1. LUTs are cmssw 200. Firmware all chips is 080408.
Key was created just before the Apr 2008 'CR0T' Global Run.
 

 



>LUT path stem will be:
bin/cmssw_2_0_0

> STATIC CONFIG
ACT_HR VM MA 0x0001 //soft reset
CSR_SCC SP MA 0x0230 //(core vers==1):: BXA off, Q3,4 stubs allowed to core, Pre Trig==2
CSR_REQ SP MA 0x801f //trig core + singles. No DT singles
CSR_DFC DD MA 0x07ff // 7 TBINs, Zero suppr, All FFPGAs active, DT active, SP active, DDU readout mode.
CSR_BID DD MA 0x8418 //configuration date is 24/4/08
CSR_MWC SP MA 0x0002 //MS winners clock phase ==2, enable output to MS.
CSR_BSY VM MA 0x0041 //VM and DDU chip into BSY FMM mask
CSR_RDY VM MA 0x0041 //VM and DDU chip into RDY FMM mask
CSR_OSY VM MA 0x0041 //VM and DDU chip into OSY FMM mask
CSR_WOF VM MA 0x0041 //VM and DDU chip into WOF FMM mask

>TIMING CONFIG:: use timing as Mar, Apr 08 local runs
CSR_REQ VM MA 0x0000 //No extra delay for L1-req
CSR_AFD FA MA 0x0558 //ME AFD == 0x58, ME1 offset=0x5
CSR_AFD SP MA 0x0504 //ME1 offset==0x5, delay incoming MB by 0x4
CSR_PFD SP MA 0x003c //PFD ==0x3c
CSR_PFD FA MA 0x003c //PFD ==0x3c

> ETA CONFIG, leave 4 new params as their defaults, set some pointing in core logic using del-eta==5 for all extraps
CNT_ETA SP MA 0x0000 //reset ETA counter
DAT_ETA SP MA 0x0000 // ETA MIN; ME1-->ME2
DAT_ETA SP MA 0x0000 // ETA MIN; ME1-->ME3
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->ME3
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->ME4
DAT_ETA SP MA 0x0000 // ETA MIN; ME3-->ME4
DAT_ETA SP MA 0x0000 // ETA MIN; ME1-->ME2-ov
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->MB1
DAT_ETA SP MA 0x0000 // ETA MIN; ME2-->MB2 **depracated
DAT_ETA SP MA 0x007f // ETA MAX; ME1-->ME2
DAT_ETA SP MA 0x007f // ETA MAX; ME1-->ME3
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->ME3
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->ME4
DAT_ETA SP MA 0x007f // ETA MAX; ME3-->ME4
DAT_ETA SP MA 0x007f // ETA MAX; ME1-->ME2-ov
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->MB1
DAT_ETA SP MA 0x007f // ETA MAX; ME2-->MB2 **depracated
DAT_ETA SP MA 0x0005 // ETA WIN; ME1-->ME2
DAT_ETA SP MA 0x0005 // ETA WIN; ME1-->ME3
DAT_ETA SP MA 0x0005 // ETA WIN; ME2-->ME3
DAT_ETA SP MA 0x0005 // ETA WIN; ME2-->ME4
DAT_ETA SP MA 0x0005 // ETA WIN; ME3-->ME4
DAT_ETA SP MA 0x0005 // ETA WIN; ME1-->ME2-overlap **depracated

> firmware versions
SP SP 08/04/08
SP FA 08/04/08
SP DD 08/04/08
SP VM 08/04/08
CCB MAIN 05/03/07
MS MAIN 26/06/07

cmssw_200_monitor_CRC.tgz

LUTs_cmssw_2_0_0_TMB07.tgz

240408 cmssw config file